MA1916

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DC CHARACTERISTICS AND RATINGS

Parameter

Min

Max

Units

Supply Voltage

-0.5

7

V

Input Voltage

-0.3

V

Current Through Any Pin

-20

+20

mA

Operating Temperature

-55

125

°C

Storage Temperature

-65

150

°C

CE_CLK (Convolution Encoder Clock)

The CE_CLK input drives the timing of the convolution

encoder. Data is read in on CE_IN on the rising edge of

CE_CLK and output on CE_OUT on both the rising and falling

edge of CE_CLK.

Note: The output data rate is twice the input data rate.

A 50% duty cycle clock is required. If this is provided by the

CLKS output, data can be read directly from RSE_OUT to the

CE_IN input (see figure 3).

CE_OUT (Convolution Encoder Output)

This signal carries the output data from the convolution

encoder. The data rate on CE_OUT is twice that of CE_IN.

CLK_OUT (Clock Out)

CLK_OUT is a buffered output of the CLK input signal. If

CLKS is connected to CE_CLK to drive the convolution

encoder, CE_OUT can be captured on the falling edge of

CLK_OUT.

Note: Stresses above those listed may cause permanent

damage to the device. This is a stress rating only and

functional operation of the device at these conditions, or at

any other condition above those indicated in the operations

section of this specification, is not implied. Exposure to

absolute maximum rating conditions for extended periods

may affect device reliability.

Table 3: Absolute Maximum Ratings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Supply Voltage

-

4.5

5.0

5.5

V

CMOS Input High Voltage

V

CMOS Input Low Voltage

-

V

CMOS Output High Voltage

-

-

V

CMOS Output Low Voltage

-

-

0.4

V

Input Leakage Current

-10

-

10

µA

Input Pull-Down Current

-20

-

150

µA

Static Power Supply Current

-

0.1

2.5

mA

Dynamic Power Supply Current

-

3

10

mA

3. Mil-Std-883, method 5005, subgroups 1, 2, 3

Table 4: DC Electrical Characteristics

AC CHARACTERISTICS

No.

Parameter

Min.

Max.

Units

1

CLK hlgh to CLKS

-

25

ns

2

CLK high to SYZ or SZY

-

30

ns

3

SMC hold after CLK low

0

-

ns

4

SMC setup to CLK low

30

-

ns

5

MSG set up to CLKS high

10

-

ns

6

MSG hold after CLKS high

10

-

ns

7

MSG to RSE_OUT propagation delay

-

30

ns

8

CLKS to RSE_OUT (SMC low)

-

25

ns

9

CLK to CLK_OUT propagation delay

-

25

ns

10

CE_IN setup to CE_CLK hlgh

10

-

ns

11

CE_IN hold after CE_CLK high

10

-

ns

12

CE_CLK to CE_OUT

-

25

ns

13

CLK CYCLE TIME

100

-

ns

Table 5: AC Electrical Characteristics

Note: Mil-Std-883, method 5005,

subgroups 9, 10, 11