HT47C20 datasheet(19/56 Pages) HOLTEK

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HT47C20

January 18, 2000

Once a wake-up event occurs, it takes 1024 tSYS

(system clock period) to resume normal opera-

tion. In other words, a dummy period will be in-

serted after the wake-up. If the wake-up results

from an interrupt acknowledgment, the actual

interrupt subroutine execution is delayed by

one more cycle. If the wake-up results in the

next instruction execution, this will execute im-

mediately after a dummy period has finished.

To minimize power consumption, all the I/O

pins should be carefully managed before enter-

ing the HALT status.

Reset

· Therearethreewaysinwhicharesetmayoccur.

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different

from other chip reset conditions, since it can

perform a warm reset that just resets the PC

and SP leaving the other circuits in their origi-

nal state. Some registers remain unchanged

during any other reset conditions. Most regis-

ters are reset to the ²initial condition² when the

reset conditions are met. By examining the PD

and TO flags, the program can distinguish be-

tween different ²chip resets².

RESET Conditions

RES reset during power-up

RES reset during normal

operation

RES wake-up HALT

WDT time-out during normal

operation

WDT wake-up HALT

Note: ²u² means ²unchanged².

To guarantee that the system oscillator has

started and stabilized, the SST (System

Start-up Timer) provides an extra delay. There

is an extra delay of 1024 system clock pulses

when the system awakes from the HALT state

or when the system powers up.

The functional unit chip reset status are shown

below.

000H

Interrupt

Disabled

Prescaler, Divider

Cleared

WDT, RTC, Time

Base

Clear. After master

reset, begin counting

Timer/event counter Off

Input/output ports Input mode

Points to the top of

the stack

t SS T

RES

VD D

S S T T i m e - out

C h i p R es et

Reset timing chart

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