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HT47C20 Datasheet(PDF) 30 Page - Holtek Semiconductor Inc

Part # HT47C20
Description  8-Bit Microcontroller
PDF  56 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT47C20 Datasheet(HTML) 30 Page - Holtek Semiconductor Inc

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HT47C20
30
January 18, 2000
LCD display memory
The HT47C20 provides an area of embedded
data memory for LCD display. The LCD display
memory is designed into 20´4 bits. If the LCD
selected 19´4 segments output, the 53H of the
LCD display memory can not be accessed. This
area is located from 40H to 53H of the RAM at
Bank 1. Bank pointer (BP; located at 04H of the
data memory) is the switch between the gen-
eral data memory and the LCD display mem-
ory. When the BP is set ²1² any data written
into 40H~53H will effect the LCD display (indi-
rect addressing mode using MP1). When the BP
is cleared ²0², any data written into 40H~53H
means to access the general purpose data mem-
ory. The LCD display memory can be read and
written only by indirect addressing mode using
MP1. When data is written into the display
data area, it is automatically read by the LCD
driver which then generates the corresponding
LCD driving signals. To turn the display on or
off, a ²1² or a ²0² is written to the corresponding
bit of the display memory, respectively. The fig-
ure illustrates the mapping between the dis-
play memory and LCD pattern for the
HT47C20.
LCD driver output
The output number of the HT47C20 LCD driver
can be 20´3or19´4 by mask option (i.e., 1/3 duty or 1/4
duty).
The bias type of the LCD driver is ²C² type. A ca-
pacitor mounted between C1 and C2 pins is
needed. The bias voltage of the LCD driver can be
1/2 bias or 1/3 bias by mask option. If 1/2 bias is
selected, a capacitor mounted between V3 pin
and the ground is required. If 1/3 bias is selected,
two capacitors are needed for V1 and V3 pins.
Refer to the application diagram.
40H
CO M
0
SEG M E N T
41H
42H
43H
51H
52H
53H
Bi t
0
1
2
3
0
1
2
3
17
18
19
1
2
3
Display memory (bank 1)
C1
C2
V1
V2
V3
C1
C2
V1
V3
1/ 3 bi as
1/ 2 bi as
V DD
V2
V DD
V1, V2, V3 application diagram



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