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HT47C20 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc |
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HT47C20 Datasheet(HTML) 28 Page - Holtek Semiconductor Inc |
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28 / 56 page ![]() HT47C20 28 January 18, 2000 Q D CK Q Da t a B u s WR WEA K Pu l l - u p PA0 / B Z V DD Ma s k Op t i o n V DD M U X M U X BZ O p t i o n R ead P a t h B Z S i gnal Q D CK Q WEA K Pu l l - u p PA1 / B Z V DD Ma s k Op t i o n V DD M U X BZ O p t i o n R ead P a t h S C h i p R es et S M U X M a sk O p t i o n S y s t em W ak e- up M a sk O p t i o n S y s t em W ak e- up Da t a B u s WR C h i p R es et PA0/BZ, PA1/BZ input/output port Input/output ports There are 8-bit bidirectional input/output port and 4-bit input port in the HT47C20, labeled PA and PB which are mapped to the data memory of [12H] and [14H] respectively. The high nibble of the PA is NMOS output and input with pull-high resisters. The low nibble of the PA can be used for input/output or output operation by selecting NMOS or CMOS output by mask op- tion. Each bit on the PA can be configured as a wake-up input, and the low nibble of the PA with or without pull-high resistor by mask op- tion. PB can only be used for input operation, and each bit on the port can be configured with pull high resistor by mask option. Both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction ²MOV A, [m]² (m=12H or 14H). For PA output operation, all data are latched and remain unchanged un- til the output latch is rewritten. When the structures of PA are open drain NMOS type, it should be noted that, before reading data from the pads, a ²1² should be written to the related bits to disable the NMOS device. That is done first before executing the instruction ²MOV A, 0FFH² and ²MOV [12H], A² to disable related NMOS device, and then ²MOV A, [12H]² to get stable data. After chip reset, these input lines remain at a high level or are left floating (by mask option). Some instructions first input data and then fol- low the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the ac- cumulator. Each bit of the PA output latches can not use these instruction, which may change the input lines to output lines (when in- put line is at low level). |
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