28F016SA datasheet(15/55 Pages) INTEL

15 / 55 page

28F016SA

4.3

28F008SA–Compatible Mode Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Notes

Oper

Addr

Data(4)

Oper

Addr

Data

Read Array

Write

xxFFH

Read

Intelligent Identifier

Write

xx90H

Read

Read Compatible Status Register

Write

xx70H

Read

CSRD

Clear Status Register

Write

xx50H

Word/Byte Program

Write

xx40H

Write

Alternate Word/Byte Program

Write

xx10H

Write

Block Erase/Confirm

Write

xx20H

Write

xxD0H

Erase Suspend/Resume

Write

xxB0H

Write

xxD0H

ADDRESS

DATA

A = Array Address

AD = Array Data

BA = Block Address

CSRD = CSR Data

IA = Identifier Address

ID = Identifier Data

PA = Program Address

PD = Program Data

X = Don’t Care

NOTES:

Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

The CSR is automatically available after device enters data program, block erase, or suspend operations.

Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.

The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.

See Status Register definitions.

28F016SA Datasheet(PDF) 15 Page - Intel Corporation

28F016SA Datasheet(HTML) 15 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL