80C187 datasheet(23/30 Pages) INTEL

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80C187

Timing Responses

All timings are measured at 15V unless otherwise specified

125 MHz

16 MHz

Test

Symbol

Parameter

Min

Max

Min

Max

Conditions

(ns)

Trhqz (t27)

NPRD Inactive to Data Float

Note 2

Trlqv (t28)

NPRD Active to Data Valid

Note 3

Tilbh (t29)

ERROR Active to Busy Inactive

104

Note 4

Twlbv (t30)

NPWR Active to Busy Active

Note 4

Tklml (t31)

NPRD or NPWR Active

Note 5

to PEREQ Inactive

Trhqh (t32)

Data Hold from NPRD Inactive

Note 3

Trlbh (t33)

RESET Inactive to BUSY Inactive

NOTES

The data float delay is not tested

2 The float condition occurs when the measured output current is less than IOL on D15–D0

3 D15–D0 loading CL e 100 pF

4 BUSY loading CL e 100 pF

5 On last data transfer of numeric instruction

Clock Timings

125 MHz

16 MHz

Test

Symbol

Parameter

Min

Max

Min

Max

Conditions

(ns)

Tclcl

(t1a)

CLK Period

CKM e 1

250

Note 6

(t1B)

CKM e 0

125

3125

125

Note 6

Tclch

(t2a)

CLK Low Time

CKM e 1

Note 6

(t2b)

CKM e 0

Note 7

Tchcl

(t3a)

CLK High Time

CKM e 1

Note 6

(t3b)

CKM e 0

Note 8

Tch2ch1(t4)

Note 9

Tch1ch2(t5)

Note 10

NOTES

16 MHz operation is available only in divide-by-2 mode (CKM strapped LOW)

6 At 15V

7 At 08V

8 At 20V

9 CKM e 1 37V to 08V at 16 MHz 35V to 10V at 125 MHz

10 CKM e 1 08V to 37V at 16 MHz 10V to 35V at 125 MHz

80C187 Datasheet(PDF) 23 Page - Intel Corporation

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