80C187 datasheet(29/30 Pages) INTEL

29 / 30 page

80C187

80C187 Extensions to the 80C186 Instruction Set

(Continued)

Encoding

Clock Count Range

Instruction

Byte

Optional

32-Bit

64-Bit

16-Bit

Bytes 2 – 3

Real

Integer

Real

Integer

CONSTANTS

(Continued)

FLDL2E e

Load log2(e) into ST(0)

ESC 001

1110 1010

FLDLG2 e

Load log10(2) into ST(0)

ESC 001

1110 1100

FLDLN2 e

Load loge(2) into ST(0)

ESC 001

1110 1101

ARITHMETIC

FADD e

Add

Integerreal memory with ST(0)

ESC MF 0

MOD 000 RM

DISP

44 – 52

77 – 92

65 – 73

77 – 91

ST(i) and ST(0)

ESCdP0

11000 ST(i)

25 – 33b

FSUB e

Subtract

Integerreal memory with ST(0)

ESC MF 0

MOD 10 R RM

DISP

44 – 52

77 – 92

65 – 73

77 – 91c

ST(i) and ST(0)

ESCdP0

1110 R RM

28 – 36d

FMUL e

Multiply

Integerreal memory with ST(0)

ESC MF 0

MOD 001 RM

DISP

47 – 57

81 – 102

68 – 93

82 – 93

ST(i) and ST(0)

ESCdP0

1100 1 RM

31 – 59e

FDIV e

Divide

Integerreal memory with ST(0)

ESC MF 0

MOD 11 R RM

DISP

108

140 – 147f

128

142 – 146g

ST(i) and ST(0)

ESCdP0

1111 R RM

90h

FSQRTi e

Square root

ESC 001

1111 1010

124 – 131

FSCALE e

Scale ST(0) by ST(1)

ESC 001

1111 1101

69 – 88

FPREM e

Partial remainder of

ST(0) d ST(1)

ESC 001

1111 1000

76 – 157

FPREM1 e

Partial remainder

(IEEE)

ESC 001

1111 0101

97 – 187

FRNDINT e

Round ST(0)

to integer

ESC 001

1111 1100

68 – 82

FXTRACT e

Extract components

of ST(0)

ESC 001

1111 0100

72 – 78

FABS e

Absolute value of ST(0)

ESC 001

1110 0001

FCHS e

Change sign of ST(0)

ESC 001

1110 0000

26 – 27

Shaded areas indicate instructions not available in 8087

NOTES

b Add 3 clocks to the range when d e 1

c Add 1 clock to each range when R e 1

d Add 3 clocks to the range when d e 0

e typical e 54 (When d e 0 48 – 56 typical e 51)

f Add 1 clock to the range when R e 1

g 153 – 159 when R e 1

h Add 3 clocks to the range when d e 1

i b0 s ST(0) s a %

80C187 Datasheet(PDF) 29 Page - Intel Corporation

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