CS82C85 datasheet(8/21 Pages) INTERSIL

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edge after FAST command recognition. Proper CLK and

CLK 50 phase relationships are maintained and minimum

pulse width specifications are met.

FAST-to-SLOW or SLOW-to-FAST mode changes will occur

on the next rising or falling edge of PCLK. It is important to

remember that the transition time for operating frequency

changes, which are dependent upon PCLK, will vary with the

82C85 oscillator or EFI frequency.

Slow Mode Control

The 82C55A programmable peripheral interface can be

used to provide control of the SLO/FST pin by connecting a

port pin of the 82C55A directly to the SLO/FST pin (See Fig-

ure 1). With the port pin configured as an output, software

control of the SLO/FST pin is provided by simply writing a

logical one (FAST mode) or logical zero (SLOW Mode) to

the corresponding port. PORT C is well-suited for this func-

tion due to it’s bit set and reset capabilities. Since PCLK con-

tinues to run at a frequency equal to the oscillator or EFI

frequency divided by 6, it can be used by other devices in

the system which need a fixed high frequency clock. For

example, PCLK could be used to clock an 82C54 program-

mable interval timer to produce a real-time clock for the sys-

tem or as a baud rate generator to maintain serial data

communications during SLOW mode operation.

Oscillator

The oscillator circuit of the 82C85 is designed primarily for

use with an external parallel resonant, fundamental mode

crystal from which the basic operating frequency is derived.

The crystal frequency should be selected at three times the

required CPU clock. X1 and X2 are the two crystal input con-

nections. The output of the oscillator is buffered and avail-

able at the OSC output (pin 18) for generation of other

system timing signals.

For the most stable operation of the oscillator (OSC) output

circuit, two capacitors (C1 = C2) are recommended. Capaci-

tors C1 and C2 are chosen such that their combined capaci-

tance matches the load capacitance as specified by the

crystal manufacturer. This insures operation within the fre-

quency tolerance specified by the crystal manufacturer.

The crystal/capacitor configuration and the formula used to

determine the capacitor values are shown in Figure 4. Crys-

tal Specifications are shown in Table 3.

Frequency Source Selection

The F/C input is a strapping pin that selects either the crystal

oscillator or the EFI input as the source frequency for clock

generation. If the EFI input is selected as the source, the

oscillator section (OSC output) can be used independently

for another clock source. If a crystal is not used, then crystal

input X1 (pin 23) must be tied to VCC or GND and X2 (pin

22) should be left open. If the EFI mode is not used, then EFI

(pin 20) should be tied to VCC or GND.

TABLE 3. CRYSTAL SPECIFICATIONS

PARAMETER

TYPICAL CRYSTAL

SPECIFICATION

Frequency

2.4 to 25MHz

Type of Operation

Parallel Resonant, Fund. Mode

Load Capacitance

20 or 32pF

RSERIES (Max)

35X (f = 25MHz, CL = 32pF)

66X (f = 25MHz, CL = 20pF)

•

---------------------- (Including Stray Capacitance)

(EQ. 1)

CRYSTAL

2.4 - 25MHz

FIGURE 4. 82C85 CRYSTAL CONNECTION

FIGURE 5. SLO/FST TIMING OVERVIEW

EFI

OSC

PCLK

SLO/FST

CLK

CLK50

82C85

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