AN4253 datasheet(27/44 Pages) STMICROELECTRONICS

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AN4253

HW resource initialization

Wait for FMPLL0 lock

Before FMPLL0 can be used as a system clock it is necessary to wait for the PLL lock event.

CR register in the FMPLL0 block contains S_LOCK bit that tells the LOCK status:

•

0 = FMPLL unlocked

•

1 = FMPLL locked

Usual lock time delay is around 200 µs.

Code sequence

Read FMPLL0 CR register

Test s_lock bit

If ‘0’ > wait loop to step 1

Enable peripherals needed in the startup

There is a set of peripherals that are clock gated (all peripherals having PCTL configuration

configured to run in dedicated mode. This configuration is done via pair of registers,

ME_RUN_PC0-7 and ME_PCTLx.

ME_RUN_PC[0-7] registers indicate if the peripherals are active and when they are inactive

(clock gated). The peripheral clock for a given mode transition must be configured by the

user.

Figure 13. Peripheral clock gating scheme

Default reset state

Note:

Any change in ME_RUN_PC0 will be used by all peripherals if they are not reconfigured to

use another ME_RUN_PCx register. Result can be that all peripherals, even peripherals

that are not needed, are enabled if ME_RUN_PC0 is enabled for current device state mode.

Good practice is not to use ME_RUN_PC0 register, but to configure one of the

ME_RUN_PC[1-7] and configure needed peripherals accordingly.

•

ME_RUN_PCx

No mode selected, no clock enabled to any gated peripheral

•

PCTLx

They point to ME_RUN_PC0

AN4253 Datasheet(PDF) 27 Page - STMicroelectronics