10F202 datasheet(24/88 Pages) MICROCHIP

24 / 88 page

PIC10F200/202/204/206

DS40001239F-page 24

 2004-2014 Microchip Technology Inc.

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

6.1

Using Timer0 with an External

Clock (PIC10F200/202)

When an external clock input is used for Timer0, it must

meet

certain

requirements.

The

external

clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

T0CKI

with

the

internal

phase

clocks

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-4). Therefore, it is necessary for T0CKI to be

high for at least 2 TOSC (and a small RC delay of 2

Tt0H) and low for at least 2 TOSC (and a small RC delay

of 2 Tt0H). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For

the

external

clock

meet

the

sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4 TOSC (and a small RC delay of 4

Tt0H) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they do

not violate the minimum pulse width requirement of

Tt0H. Refer to parameters 40, 41 and 42 in the

electrical specification of the desired device.

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetch

Timer0

PC + 1

PC + 2

PC + 3

PC + 4

PC + 6

T0 + 1

NT0

NT0 + 1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W

MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

PC + 5

(Program

Counter)

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

01h

TMR0

Timer0 – 8-bit Real-Time Clock/Counter

xxxx xxxx

uuuu uuuu

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

N/A

TRISGPIO(1)

—

I/O Control Register

---- 1111

Legend:

Shaded cells not used by Timer0.

– = unimplemented,

= unknown,

= unchanged.

Note

The TRIS of the T0CKI pin is overridden when T0CS = 1.

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