10F202 datasheet(40/88 Pages) MICROCHIP

40 / 88 page

PIC10F200/202/204/206

DS40001239F-page 40

 2004-2014 Microchip Technology Inc.

9.5

Device Reset Timer (DRT)

On the PIC10F200/202/204/206 devices, the DRT runs

any time the device is powered-up.

The DRT operates on an internal oscillator. The

processor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

The on-chip DRT keeps the devices in a Reset

condition for approximately 18 ms after MCLR has

reached a logic high (VIH MCLR) level. Programming

GP3/MCLR/VPP as MCLR and using an external RC

network connected to the MCLR input is not required in

most cases. This allows savings in cost-sensitive and/

or space restricted applications, as well as allowing the

use of the GP3/MCLR/VPP pin as a general purpose

input.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 9.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

9.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

internal 4 MHz oscillator. This means that the WDT will

run even if the main processor clock has been stopped,

for example, by execution of a SLEEP instruction.

During normal operation or Sleep, a WDT Reset or

wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The

WDT

can

permanently

disabled

programming the configuration WDTE as a ‘0’ (see

Section 9.1 “Configuration Bits”). Refer to the

PIC10F200/202/204/206 Programming Specifications

to determine how to access the Configuration Word.

9.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These

periods vary with temperature, VDD and part-to-part

process variations (see DC specs).

Under worst-case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

9.6.2

WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

TABLE 9-3:

DRT PERIOD

Oscillator

POR Reset

Subsequent

Resets

INTOSC

18 ms (typical)

s (typical)

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