| Electronic Components Datasheet Search |
|
AN4350 Datasheet(PDF) 8 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN4350 Datasheet(HTML) 8 Page - STMicroelectronics |
|
8 / 34 page ![]() Circuit description and design guidelines AN4350 8/34 DocID025181 Rev 1 2.3 Output voltage control - primary side regulation The IC is specifically designed to work in a primary side regulation (PSR) and the output voltage is sensed through a voltage partition of the auxiliary winding, as shown in Figure 3. The signal on the DMG pin is sampled-and-held at the end of transformer demagnetization to get an accurate image of the output voltage (VOUT) and it is compared with the internal error amplifier reference voltage VREF (2.51 V typ.). During the MOSFET's OFF-time the leakage inductance resonates with the drain capacitance and a damped oscillation is superimposed on the reflected voltage. The internal S/H logic is able to discriminate such oscillations from the real transformer demagnetization. When the DMG logic detects the transformer demagnetization, the sampling process stops, the information is frozen and compared with the error amplifier internal reference. The internal error amplifier is a transconductance type and delivers on the COMP pin a current proportional to the voltage unbalance of the two inputs: the COMP pin generates the control voltage that is compared with the voltage across the sense resistor, thus modulating the cycle-by-cycle peak drain current to regulate the desiderated output voltage. Figure 3. Voltage control principle: internal schematic The COMP pin is used for the frequency compensation: typically an RC - CC network, which stabilizes the overall voltage control loop, is connected between this pin and ground. When implementing the high power factor (HPF - see Section 2.4: High power factor implementation), the output voltage control loop must have frequency bandwidth much lower than the “control current loop” (100/120 Hz, that is the double of line input frequency). As a consequence the output voltage control loop has to be designed in order to have bandwidth much lower than 100/120 Hz (i.e. BWCV < 5 - 10 Hz). |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |