AN4350 datasheet(14/34 Pages) STMICROELECTRONICS

14 / 34 page

Circuit description and design guidelines

AN4350

14/34

DocID025181 Rev 1

Equation 26

Equation 27

where ESR is the equivalent output capacitor resistance and dp is the primary duty-cycle

that depends on the input and output voltage and it can be estimated with Equation 28:

Equation 28

The power stage presents one pole at low frequency (this pole is basically related to the

output filter time constant), and two zeros. Note that one zero is positive, resulting in

a negative contribution on the phase margin.

Replacing the component value on Equation 25, Equation 26, Equation 27 and considering

the VinRMS_typ and IOUTMAX, the frequency singularities of the power stage result:

The feedback gain transfer function is the ration between the output voltage and the DMG

pin, and it is calculated using Equation 29:

Equation 29

The sample and hold transfer function can be neglected because system voltage loop

bandwidth is much lower than the system switching frequency (the pole of the sample and

hold circuitry is at higher frequency than system bandwidth BWCV << FpS&H):

Equation 30

Gsh(s)

1

Typically an RC - CC series network is connected between the COMP pin and ground to

compensate the system loops, resulting in the following error amplifier transfer function:

Equation 31

Equation 32

fp_ps = 2.6 Hz

fz1_ps = 2.5 kHz

fz2_ps = 183 kHz.

z2 ps

-------





ROUT 1dP

–





LP dP



------------------------------------------------------------------

pps

1dP

ROUT COUT



------------------------------------

VR  VinRMS



-------------------------------------------

Gfb

NAUX

--------------

RFB

RFB RDMG

---------------------------------



Gea s



Gea0

zea

-----------------





---------------------------------



Gea0

--------

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