LCD drive signals

AN2687

8/22

Doc ID 14296 Rev 1

Figure 4.

LCD timing diagram for quadruplex mode

2.1.1

LCD mean voltage calculation

The LCD mean voltage must be very close to zero to guarantee long life to the LCD. The

LCD mean voltage for On and Off periods can be calculated as shown below:

(1)

Vmean(Off) = 3(Vseg/2) + 3(–Vr/2)

(2)

Vmean(On) and Vmean(Off) assume identical periods for each phase.

Equating equations (1) & (2) to zero, that is putting Vmean(On) = 0 and Vmean(Off) = 0,

gives:

●

●

Vr/2 is the voltage in the middle of the resistor bridge, applied on the COM line

●

Vseg is the maximum voltage on the Segx line

●

COM1

ai15954

COM2

Segx_1 On

Segx_2 Off

Segx_3 On

Segx_4 Off

T/8

T/4

T/2

3T/4

T

COM3

COM4

Vsegx

Control

period

Single-frame period

LCD

COM1

COM2

COM3

COM4

SEG1