AN2797

DDR memory interface

Doc ID 14841 Rev 1

11/23

Trace length matching. Additionally, matching the length of the branch traces to each DRAM

is necessary. Mismatches in the branch length rapidly degrade signal integrity. The branch

lengths, and therefore the spacing between two memory devices, should be minimized.

Figure 2 (A, B, C) below and Table 2 describe the length matching guidelines for a dual

DRAM topology.

Note:

This is a guideline only, simulations should be performed using IBIS models on the actual

PCB layout to assess signal integrity and timing margin.

Figure 2.

Dual DRAM "T" routing topology

Figure 2 (A) shows the topology of the data signals, Figure 2 (B) shows the topology of the

address/command/control signals with optional shunt terminations, the Figure 2 (C) shows

the topology of the differential signal CLK and DQS. Table 2 lists guidelines for length

matching of the various segments.

2.5

Return path integrity

A continuous path for return current must exist for all DRAM signals. If not, signal delays,

significant crosstalk, and timing violations may likely result.

Table 2.

Trace length matching guidelines, dual DRAM configuration

Symbol

Description

Max

Units

tmm

L1 +L2, L1+L3 length matching for all signals

15

ps

Tmm2,3

|L2-L3| length matching tolerance of branches

30

ps