DDR memory interface

AN2797

12/23

Doc ID 14841 Rev 1

Signal layer changes: The preferred location for layer change vias are near the signal ball

under the device, either DRAM or SPEAr, enabling a signal return path through the device

ground vias and decoupling capacitors.

If layer changes through a via to a different reference plane are necessary away from the

devices, the layer transitions should have a nearby path for return current. If both layers are

ground, a ground via should be placed less than 1 mm from the signal via. Sharing return

current vias should be avoided. Each signal via should have its own nearby return via

(ground via). If multiple signals change layers in close proximity, each signal via should have

its own return current via. So, signal vias (and their return current vias) should be separated

from other signal vias with a stagger pattern. If routing density prevents a stagger pattern,

add as many ground vias as possible among the signal vias.

2.6

Clock routing

The clock differential signals should be routed with a pair of matched length symmetrical

traces with 110 Ohm differential impedance. The preferred clock routing layer is the top layer

with no layer transitions. The termination layout should be symmetrical, without stubs, and

located as close as possible to the clock balls on the DRAM. Three termination topologies

are shown in Figure 3. Termination resistors and decoupling capacitors should be placed in

a tight orientation to minimize trace lengths. Termination components should not share vias.

The decoupling capacitor should have a via to ground placed against the side of its ground

land. Figure 3 shows three clock termination topology options. The middle topology provides

the best tradeoff between part count and common mode rejection.

Figure 3.

Clock termination topology options

2.7

Vref routing

An accurate and quiet Vref should be provided to both the DRAM and the controller. A noisy

Vref effectively introduces jitter because of this it can be a significant source of jitter-caused

timing errors. Vref is generated by a precision voltage divider. Recommended: use 0.1%

tolerance resistors. A decoupling capacitor should be placed very close (within 1 mm) to the

Vref balls. Use good capacitor layout technique. The voltage divider resistors should be

placed close to the DRAM device to minimize trace length, but not so they interfere with

other critical signal or power routing. The Vref trace should not be routed near noisy traces