Low-inductance decoupling capacitor layout

AN2797

20/23

Doc ID 14841 Rev 1

Appendix A

Low-inductance decoupling capacitor layout

This appendix provides guidelines for low-inductance capacitor layout for high-frequency

decoupling applications.

Figure 8 shows various layouts for decoupling capacitors. The layouts shown in (a) and (b)

have inherently high inductance, and thus a high impedance at high frequencies and should

be avoided.

The layouts in (d) and (e) have low inductance and should be used for high frequency

decoupling applications. The 4-via layout (e) has the lowest inductance (but requires more

board area), and should be used where space allows. The 2-via layout shown in (d) is a

good compromise when space does not permit the 4-via layout. The layout shown in (c)

should be used as a last resort when there is no space for (d) or (e).

Figure 8.

Decoupling capacitor layouts

A.1

0402 compact land pattern

A area-efficient compact land pattern facilitates PCB layout of decoupling capacitors.

Figure 9 shows a commonly used land pattern.

Figure 9.

Compact layout for 0402 size package