2.2

Memory controller

The memory controller is a set of registers to control the RAM and DMA memories, these registers are required for low power

mode, however before entering in low power modes the user needs to save the context for all the memory controller registers and

restore these configurations after the wake up from the low power modes. In revision 13 of the datasheet, the memory controller is

not documented.

2.2.1

STM32W108xx MEM bits and registers overview

Table 4 gives the memory controller bits and registers naming.

Table 4.

Memory controller bits and registers overview

Register

STM32W108xx MEM Controller bits/registers naming overview

0x5000

RAM_PROTR1

[31:0]

0x5004

RAM_PROTR2

[31:0]

0x5008

RAM_PROTR3

[31:0]

0x500C

RAM_PROTR4

[31:0]

0x5010

RAM_PROTR5

[31:0]

0x5014

RAM_PROTR6

[31:0]

0x5018

RAM_PROTR7

[31:0]

0x501C

RAM_PROTR8

[31:0]

0x5020

DMA_PROTR1

OFFSET

ADDRESS

0x5024

DMA_PROTR2

Reserved

CHANNEL

0x5028

RAM_CR

Reserved

WEN

Reserved