8

Interrupts

The STM32W108xx microcontrollers are based on the core Cortex-M3, so the nested vectored interrupt controller (NVIC) registers

section is removed from the datasheet and a reference to the Cortex-M3 programming manual.pdf (PM0056) is added to make the

library compliant with the Cortex™ microcontroller software interface standard (CMSIS)

8.1

STM32W108xx NVIC Overview

Table 17 gives the compatibility guideline between the NVIC registers section presented in datasheet Rev13 and the equivalent

one in the Cortex-M3 programming manual.

The bits and registers definitions for the Cortex-M3 Core Peripheral Access Layer are provided in the CMSIS library under:

CMSIS\Include\core_cm3.h file

Table 17.

NVIC bits and registers overview

Offset

0xA820

0xE100

0xE180

0xE200

0xE280

0xE300

0xED3C

Register

INT_

MISS

Res

INT_

CFGSET

NVIC_

ISER

INT_CFG

CLR

NVIC_

ICER

INT_PEN

DSET

NVIC_

ISPR

INT_PEN

DCLR

NVIC_

ICPR

INT_

ACTIVE

NVIC_

IABR

SCS_

AFSR

SCB_

AFSR

Bit 31-17 Reserved

Reserved

Reserved

Bit 16

INT_

DEBUG

INT_

DEBUG

DEBUG

INT_

DEBUG

DEBUG

INT_

DEBUG

DEBUG

INT_

DEBUG

DEBUG

INT_

DEBUG

DEBUG

Bit 15

INT_

IRQD

INT_

IRQD

IRQD

INT_

IRQD

IRQD

INT_

IRQD

IRQD

INT_

IRQD

IRQD

INT_

IRQD

IRQD

Bit 14

INT_

IRQC

INT_

IRQC

IRQC

INT_

IRQC

IRQC

INT_

IRQC

IRQC

INT_

IRQC

IRQC

INT_

IRQC

IRQC

Bit 13

INT_

IRQB

INT_

IRQB

IRQB

INT_

IRQB

IRQB

INT_

IRQB

IRQB

INT_

IRQB

IRQB

INT_

IRQB

IRQB

Bit 12

INT_

IRQA

INT_

IRQA

IRQA

INT_

IRQA

IRQA

INT_

IRQA

IRQA

INT_IRQA

IRQA

INT_I

RQA

IRQA

Bit 11

INT_ADC

INT_

ADC

ADC

INT_

ADC

ADC

INT_

ADC

ADC

INT_

ADC

ADC

INT_ADC

ADC