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AN4142 Datasheet(PDF) 18 Page - STMicroelectronics

Part # AN4142
Description  STM32W108xx datasheet bit and register naming migration
PDF  38 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4142 Datasheet(HTML) 18 Page - STMicroelectronics

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4
General-purpose input/outputs
The General-purpose input/output IP presented in the revision 13 of the STM32W108xx datasheet is split into three main parts:
●
Standard General-purpose input/output : GPIO
●
External interrupt: EXTI
●
Debug management: DBG
The GPIO_PAWAKE, GPIO_PBWAKE, GPIO_PCWAKE and GPIO_WAKEFILT registers are renamed respectively
PWR_WAKEPAR, PWR_WAKEPBR, PWR_WAKEPCR and PWR_WAKEFILTR registers. These registers are required to manage
the GPIO wake up resources from low power modes and will be presented in the low power mode section.
4.1
Standard General-purpose input/output
This part will contain only the GPIO configurations and status registers.
4.1.1
STM32W108xx GPIO Overview
Table 11 gives the list of the changes (renaming) made in the GPIO bits and registers.
Table 11.
GPIO bits and registers overview
Offset
(GPIOA/
GPIOB/
GPIOC)
Register
STM32W108xx GPIO bits/registers naming overview
0x00
GPIO_PxCFGL
Res
Px3_CFG
Px2_CFG
Px1_CFG
Px0_CFG
GPIOx_CRL
Res
CNFMODE3[3:0]
CNFMODE2[3:0]
CNFMODE1[3:0]
CNFMODE0[3:0]
0x04
GPIO_PxCFGH
Res
Px7_CFG
Px6_CFG
Px5_CFG
Px4_CFG
GPIOx_CRH
Res
CNFMODE7[3:0]
CNFMODE6[3:0]
CNFMODE5[3:0]
CNFMODE4[3:0]
0x08
GPIO_PxIN
Reserved
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
GPIOx_IDR
Reserved
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0



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