DocID026505 Rev 1

11/25

AN4538

STM32F3xx microcontroller low-power overview

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1.4.2

Low-power features

Some STM32F3xxxx peripherals have low-power features which facilitate the use of low-

power modes while maintaining a high processing capability. The availability of these

features differs between the STM32F3xx microcontrollers.

•

COMP

The STM32F3xxxx comparators work independently from the PCLK2 clock. Thanks to

this clock, the comparators can even operate in Stop mode. Each comparator has its

own EXTI line and can generate either interrupts or events, which can wake up the

device from both Sleep and Stop modes.

The outputs can be connected to an I/O or to multiple timer inputs in order to trigger

control and monitor analog signals during Sleep mode.

The comparator power consumption versus speed can be adjusted to have the

optimum trade-off for a given application (This feature is available only in the

STM32F303/302xB/C, STM32F358xx, STM32F373xx and STM32F378xx devices.).

•

U(S)ART

All U(S)ART interfaces can be served by the DMA controller during Sleep mode.

USART supports a dual clock domain which allows the functionality and wake up from

Stop mode. USART can wake up from Stop mode via either address match, start bit or

by RXNE when its clock source is HSI or LSE.

Such feature facilitates the design and development of the application while

maintaining the power efficiency.

Note that the user can put the IrDA SIR ENDEC in low-power mode to save more

power.

•

I2C

DMA can be used to reduce CPU overload and thus the power consumption. The I2C

is clocked by an independent clock source which allows the I2C to operate

independently from the PCLK frequency. When the I2C clock source is the HSI, the I2C

can wake up from Stop mode on address match.

•

CEC

Consumer Electronics Control protocol can operate at low speeds with a minimum

processing and memory overhead. It has a clock domain independent from the CPU

clock, allowing to wake up the MCU from Stop mode on data reception.

HDMI_CEC controller is embedded only in STM32F37xxx devices.

•

ADC

The STM32F3xxxx devices (except for STM32F373/378xx devices) embed a low-

power ADC which consumption is proportional to the speed. The lowest consumption is

got with the lowest speed.

This ADC has two clock sources derived from AHB and PLLCLK clocks. Consequently,

the max speed 5MSPS can be reached even with a slow AHB bus frequency. In this

case, ADC auto-delayed feature is available in order to avoid ADC overruns.