5V, Low-Power, Voltage-Output

Serial 10-Bit DACs

8

_______________________________________________________________________________________

10

FUNCTION

1

BIPOFF

Bipolar offset/gain

resistor

2

DIN

Serial data input

3

CLR

Clear. Asynchronously sets

DAC register to all 0s.

PIN

—

1

4

SCLK

Serial clock input

5

CS

Chip select, active low

6

DOUT

Serial data output for

daisy-chaining

7

DGND

Digital ground

—

2

3

8

AGND

Analog ground

9

REFIN

Reference input

4

—

5

6

—

REFOUT

Reference output,

if not used.

11

—

Negative power supply

12

7

VOUT

DAC output

13

8

Positive power supply

14

—

RFB

Feedback resistor

MAX504

MAX515

NAME

____________________Pin Description

_______________Detailed Description

General DAC Discussion

The MAX504/MAX515 use an “inverted” R-2R ladder net-

work with a single-supply CMOS op amp to convert 10-bit

digital data to analog voltage levels (see

Functional

Diagram). The term “inverted” describes the ladder net-

work because the REFIN pin in current-output DACs is the

summing junction, or virtual ground, of an op amp.

However, such use would result in the output voltage

being the inverse of the reference voltage. The

MAX504/MAX515’s topology makes the output the same

polarity as the reference input.

An internal reset circuit forces the DAC register to reset

to all 0s on power-up. Additionally, a clear (CLR) pin,

when held low, sets the DAC register to all 0s. CLR

operates asynchronously and independently from the

chip select (CS) pin.

Buffer Amplifier

The output buffer is a unity-gain stable, rail-to-rail output,

BiCMOS op amp. Input offset voltage and CMRR are

trimmed to achieve better than 10-bit performance.

Settling time is 25µs to 0.01% of final value. The output is

short-circuit protected and can drive a 2k

Ω load with more

than 100pF load capacitance.

CS

SCLK

DIN

DOUT

Figure 1. Timing Diagram