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ZL6105ALAF Datasheet(PDF) 25 Page - Intersil Corporation

Part # ZL6105ALAF
Description  Digital DC/DC Controller with Drivers and Auto Compensation
PDF  35 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ZL6105ALAF Datasheet(HTML) 25 Page - Intersil Corporation

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ZL6105
25
FN6906.5
December 19, 2013
2. Ratiometric. This mode configures the ZL6105 to ramp its
output voltage at a rate that is a percentage of the voltage
applied to the VTRK pin. The default setting is 50%, but an
external resistor string may be used to configure a different
tracking ratio.
Figure 15 illustrates the typical connection and the two tracking
modes.
The master ZL6105 device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode. A delay
of at least 10ms must be configured into the master device using
the SS pin, and the user may also configure a specific ramp rate
using the SS pin. Any device that is configured for tracking mode
will ignore its soft-start delay and ramp time settings (SS pin) and
its output will take on the turn-on/turn-off characteristics of the
reference voltage present at the VTRK pin. All of the ENABLE pins
in the tracking group must be connected together and driven by a
single logic source. Tracking is configured via the I2C/SMBus
interface by using the TRACK_CONFIG PMBus command. Please
refer to Application Note AN2033 for more information on
configuring tracking mode using PMBus.
When a current sharing rail is tracking, the on-delay time of the
voltage being tracked must not exceed the on-delay of the
tracking rail by 5ms.
Voltage Margining
The ZL6105 offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. The MGN command is set by driving the
MGN pin or through the I2C/SMBus interface. The MGN pin is a
tri-level input that is continuously monitored and can be driven
directly by a processor I/O pin or other logic-level output.
The ZL6105’s output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output will
be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of VNOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I2C/SMBus interface to as high as VNOM + 10% or as
low as 0V, where VNOM is the nominal output voltage set point
determined by the V0 and V1 pins. The ZL6105-01 allows 150%
margin limits.
The margin limits and the MGN command can both be set
individually through the I2C/SMBus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I2C interface. Please
refer to Application Note AN2033 for detailed instructions on
modifying the margining configurations.
I2C/SMBus Communications
The ZL6105 provides an I2C/SMBus digital interface that enables
the user to configure all aspects of the device operation as well
as monitor the input and output parameters. The ZL6105 can be
used with any standard 2-wire I2C host device. In addition, the
device is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
I2C/SMBus as specified in the SMBus 2.0 specification. The
ZL6105 accepts most standard PMBus commands. When
controlling the device with PMBus commands, it is
recommended that the enable pin is tied to SGND.
I2C/SMBus Device Address Selection
When communicating with multiple SMBus devices using the
I2C/SMBus interface, each device must have its own unique
VOUT
VOUT
Time
Coincident
Ratiometric
VTRK
VIN
VOUT
Q1
Q2
L1
C1
GH
GL
SW
ZL
VTRK
VOUT
VOUT
Time
VTRK
FIGURE 15. TRACKING MODES
TABLE 20. TRACKING RESISTOR SETTINGS
RSS
(k
Ω)
TRACK
RATIO
(%)
UPPER TRACK
LIMIT
RAMP-UP/DOWN BEHAVIOR
90.9
100
Limited by target
Output does not decrease
before PG
100
Output always follows VTRK
110
Limited by VTRK
Output does not decrease
before PG
121
Output always follows VTRK
133
50
Limited by target
Output does not decrease
before PG
147
Output always follows VTRK
162
Limited by VTRK
Output does not decrease
before PG
178
Output always follows VTRK



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