PIC18LC658 datasheet(97/366 Pages) MICROCHIP

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 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 97

PIC18CXX8

8.5

PORTE, TRISE and LATE Registers

PORTE is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISE. Setting a

TRISE bit (=1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

hi-impedance mode). Clearing a TRISE bit (=0) will

make the corresponding PORTE pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATE register

reads and writes the latched output value for PORTE.

PORTE is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output. PORTE is multiplexed with several peripheral

functions (Table 8-9).

EXAMPLE 8-5:

INITIALIZING PORTE

FIGURE 8-8:

PORTE BLOCK DIAGRAM

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

0x03

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE1:RE0 as inputs

; RE7:RE2 as outputs

Peripheral Out Select

Data Bus

WR LATE

WR TRISE

Data

Latch

TRIS Latch

RD TRISE

Peripheral Data Out

VDD

VSS

RD PORTE

Peripheral Data In

I/O Pin(1)

WR PORTE

RD LATE

Schmitt

Trigger

Note 1:

I/O pins have diode protection to VDD and VSS.

TRIS OVERRIDE

Override

Peripheral

RE0

Yes

PSP

RE1

Yes

PSP

RE2

Yes

PSP

RE3

—

RE4

—

RE5

—

RE6

—

RE7

—

TRIS

Override

Peripheral Enable

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