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PIC18LC658-E/CL Datasheet(PDF) 93 Page - Microchip Technology

Part # PIC18LC658-E/CL
Description  High-Performance Microcontrollers with CAN Module
PDF  366 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18LC658-E/CL Datasheet(HTML) 93 Page - Microchip Technology

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 2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 93
PIC18CXX8
8.3
PORTC, TRISC and LATC Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the correspond-
ing peripheral section for the correct TRIS bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 8-3:
INITIALIZING PORTC
FIGURE 8-6:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISC
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
Peripheral Out Select
Data Bus
WR LATC
WR TRISC
Data
Latch
TRIS Latch
RD TRISC
Q
D
Q
CK
QD
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
VDD
VSS
RD PORTC
Peripheral Data In
I/O Pin
or
WR PORTC
RD LATC
Schmitt
Trigger
Note:
I/O pins have diode protection to VDD and VSS.
TRIS
Override
Peripheral Enable
TRIS OVERRIDE
Pin
Override
Peripheral
RC0
Yes
Timer1 OSC for Timer1/Timer3
RC1
Yes
Timer1 OSC for Timer1/Timer3
RC2
No
—
RC3
Yes
SPI/I2C Master Clock
RC4
Yes
I2C Data Out
RC5
Yes
SPI Data Out
RC6
Yes
USART Async Xmit, Sync Clock
RC7
Yes
USART Sync Data Out



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