TPS54341_15 datasheet(13/48 Pages) TI

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OUT(max)

(max)

IN(min)

OUT(max)

DS(on)

OUT(max)

x (V

- I

x R

V ) - V

x R

TPS54341

www.ti.com

SLVSC61 – NOVEMBER 2013

DETAILED DESCRIPTION (continued)

When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.

Because the device is not switching, the output voltage begins to decay. The voltage-control loop responds to

the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching

resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to

the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the

device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light

load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54341 device senses and controls peak switch current, not the average

load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor

value. The circuit in Figure 46 enters Eco-mode at 30-mA output current. As the load current approaches zero,

the device enters a pulse-skip mode during which it draws only 152-

μA input quiescent current.

Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54341 device provides an integrated bootstrap-voltage regulator. A small capacitor between the BOOT

and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor refreshes when the

high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT

capacitor is 0.1

μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or

higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54341

device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the

voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side

MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at

high output voltages, the low-side MOSFET is disabled at 24 V output and re-enabled when the output reaches

21.5 V.

Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET remains on for

many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of the

switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is

mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode

voltage, and the printed circuit-board resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is

plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within

1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where

switching stops.

During high duty-cycle (low dropout) conditions, inductor current-ripple increases when the BOOT capacitor

recharges resulting in an increase in output-voltage ripple. Increased ripple occurs when the off time required to

recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle PWM control.

At heavy loads, the minimum input voltage must increase to ensure a monotonic startup. Equation 1 calculates

the minimum input voltage for this condition.

(1)

where

•

D(max) ≥ 0.9

•

Vd = forward drop of the catch diode

•

VBOOT = (1.41 × VIN – 0.554 – Vd × ƒSW – 1.847 × 10

3 × IB2SW) / (1.41 + ƒ

SW)

•

R DS(on) = 1 / (–0.3 × VB2SW

2 + 3.577 × VB2SW – 4.246)

•

IB2SW = 100 µA

•

VB2SW = VBOOT + Vd

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