TPS54341_15 datasheet(22/48 Pages) TI

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TPS54341

SLVSC61 – NOVEMBER 2013

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DETAILED DESCRIPTION (continued)

Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. Once the FB pin is between 93% and 106% of the internal voltage

reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 k

Ω to a voltage source that is

5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull up

voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise

seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but

with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input

voltage approaches 3 V.

The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal

reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin

pulled low.

Overvoltage Protection

The TPS54341 device incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients in designs with low-output capacitance.

For example, when the power-supply output is overloaded the error amplifier compares the actual output voltage

to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a

considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak

current-limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier

output transitions to the normal operating level. In some applications, the power-supply output voltage increases

faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin

voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin

voltage is greater than the rising OVP threshold, the high-side MOSFET disables immediately to minimize output

overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal

voltage reference, the high-side MOSFET resumes normal operation.

Thermal Shutdown

The TPS54341 device provides an internal thermal shutdown to protect the device when the junction

temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the

thermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence

controlled by discharging the SS/TR pin.

Small-Signal Model for Loop Response

Figure 42 shows a simplified equivalent model for the TPS54341 control loop which is simulated to check the

frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA

of 350

μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor RO and

capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage source

between the nodes a and b effectively breaks the control loop for the frequency response measurements.

Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small

signal response of the overall loop. The dynamic loop response is evaluated by replacing RL with a current

source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is

only valid for CCM operation.

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