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ADP3430

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to 1.7 V. This DELAY pin is used for multiple delay timings

(TD1, TD3, and TD5) during the startup sequence. Also,

DELAY is used for timing the current limit latchoff, as

explained in the Current Limit, Short−Circuit, and Latchoff

Protection section.

Soft−Start

The soft−start times for the output voltage are set with a

capacitor from the SS pin to ground. After TD1 and the

phase detection cycle have been completed, the SS time

(TD2 in Figure 5) starts. The SS pin is disconnected from

GND, and the capacitor is charged up to the 1.1 V boot

voltage by the SS amplifier, which has a limited output

current of 15

mA. The voltage at the FB pin follows the

ramping voltage on the SS pin, limiting the inrush current

during startup. The soft−start time depends on the value of

the boot voltage and CSS.

Once the SS voltage is within 100 mV of the boot voltage,

the boot voltage delay time (TD3 in Figure 5) is started. The

end of the boot voltage delay time signals the beginning of

the second soft−start time (TD4 in Figure 5). The SS voltage

now changes from the boot voltage to the programmed VID

DAC voltage (either higher or lower) using the SS amplifier

with the limited 15

mA output current. The voltage of the FB

pin follows the ramping voltage of the SS pin, limiting the

inrush current during the transition from the boot voltage to

the final DAC voltage. The second soft−start time depends

on the boot voltage, the programmed VID DAC voltage, and

CSS.

If EN is taken low or if VCC drops below UVLO, DELAY

and SS are reset to ground to be ready for another soft−start

cycle. Figure 6 shows typical startup waveforms for the

ADP3430.

Figure 6. Typical Startup Waveform

1−Vo, 2−SS, 3−DELAY, 4−EN, D0−D3−PWM1~3

Current Limit, Short−Circuit, and Latchoff Protection

The ADP3430 compares a programmable current limit set

point to the voltage from the output of the current sense

amplifier. The level of current limit is set with the resistor

from the ILIM pin to CSCOMP. During operation, the

voltage on ILIM is equal to the voltage on CSREF. The

current through the external resistor connected between

ILIM and CSCOMP is then compared to the internal current

limit current Icl. If the current generated through this register

into the ILIM pin(ILIM) exceeds the internal current limit

threshold current (Icl), the internal current limit amplifier

controls the internal COMP voltage to maintain the average

output at the limit.

If the limit is reached and TD5 in Figure 5 has completed,

a latchoff delay time starts, and the controller shuts down if

the fault is not removed. The current limit delay time shares

the DELAY pin timing capacitor with the startup sequence

timing. However, during current limit, the DELAY pin

current is reduced to 3.75

mA. A comparator monitors the

DELAY voltage and shuts off the controller when the

voltage reaches 1.7 V. Therefore, the current limit latchoff

delay time is set by the current of 3.75

mA, charging the

delay capacitor from 0 V to 1.7 V. This delay is four times

longer than the delay time during the startup sequence.

The current limit delay time starts only after the TD5 is

complete. If there is a current limit during startup, the

ADP3430 goes through TD1 to TD5, and then starts the

latchoff time. Because the controller continues to cycle the

phases during the latchoff delay time, the controller returns

to normal operation and the DELAY capacitor is reset to

GND if the short is removed before the 1.7 V threshold is

reached.

For the same Rt value, the current limit for 2−phase

operation (PSI = Low) is 2/3 of that of 3−phase (PSI = High).

The latchoff function can be reset by either removing and

reapplying the supply voltage to the ADP3430, or by toggling

the EN pin low for a short time. To disable the short circuit

latchoff function, an external resistor should be placed in

parallel with CDLY. This prevents the DELAY capacitor from

charging up to the 1.7 V threshold. The addition of this

resistor causes a slight increase in the delay times.

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage

to the PWM comparators to 1.5 V. This limits the voltage drop

across the low−side MOSFETs through the current balance

circuitry. An inherent per−phase current limit protects

individual phases if one or more phases stop functioning

because of a faulty component. This limit is based on the

maximum normal mode COMP voltage. Typical overcurrent

latchoff waveforms are shown in Figure 6.

Output Current Monitor

The IMON pin is used to output an analog voltage

representing the total output current being delivered to the

load. It outputs an accurate current that is directly

proportional to the current set by the ILIM resistor. This

current is then run through a parallel RC connected from the

IMON pin to the FBRTN pin to generate an accurately scaled

and filtered voltage per the VR11.1 specification. The size

of the resistor is used to set the IMON scaling.

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