ADP3430 datasheet(16/26 Pages) ONSEMI

16 / 26 page

ADP3430

http://onsemi.com

Application Information

The design parameters for a typical Intel VRD 11.1

compliant CPU application are as follows:

• Input voltage (VIN) = 12 V

• VID setting voltage (VVID) = 1.51875 V

• Duty cycle (D) = 0.1266

• Nominal output voltage at no load (VONL) = 1.5 V

• Maximum output current (IO) = 69 A

• Maximum output current step (DIO) = 56 A

• Maximum output current slew rate (SR) = 50 A/ms

• Number of phases (n) = 3

• Switching frequency per phase (fsw) = 300 kHz

Setting the Clock Frequency

The ADP3430 uses a fixed frequency control architecture.

The frequency is set by an external timing resistor (RT). The

clock frequency determines the switching frequency per

phase, which relates directly to switching losses as well as

the sizes of the inductors, the input capacitors, and output

capacitors. A clock frequency of 1.8 MHz sets the switching

frequency (fsw) of each phase to 300 kHz, which represents

a practical trade−off between the switching losses and the

sizes of the output filter components. Figure 3 shows that to

achieve a 1.8 MHz oscillator frequency, the correct value for

RT is 97 kW. Alternatively, the value for RT can be calculated

using:

RT +

fosc

5.3 pF )

4.4 kW

(eq. 1)

fsw +

fosc

where 5.3 pF is the internal IC component values. For good

initial accuracy and frequency stability, a 1% resistor is

recommended.

Soft−Start Delay Time

The value of

CSS sets the soft−start time. The ramp is

generated with a 15

mA internal current source. The value for

CSS can be found using:

CSS + 15 mA

TD2

VBOOT

(eq. 2)

where TD2 is the desired soft−start time, and VBOOT is

internally set to 1.0 V.

Assuming a desired TD2 time of 2.5 ms, CSS is 37.5 nF.

The closest standard value for CSS is 39 nF. Although CSS

also controls the time delay for TD4 (determined by the final

VID voltage), the minimum specification for TD4 is 0 ns.

This means that as long as the TD2 time requirement is met,

TD4 is within the specification.

Current Limit Latchoff Delay Times

The startup and current limit delay times are determined

by the capacitor connected to the DELAY pin. The first step

is to set CDLY for the TD1, TD3, and TD5 delay times (see

Figure 5). The DELAY ramp (IDELAY) is generated using a

mA internal current source.

The value for CDLY can be approximated using:

CDLY + IDELAY

TD(x)

VDELAY(TH)

(eq. 3)

where TD(x) is the desired delay time for TD1, TD3, and

TD5. The DELAY threshold voltage (VDELAY(TH)) is given

as 1.7 V. In this example, 2 ms is chosen for all three delay

times, which meets Intel specifications. Solving for CDLY

gives a value of 17.6 nF. The closest standard value for CDLY

is 18 nF.

When the ADP3430 enters current limit, the internal

current source changes from 15

mA to 3.75 mA. This makes

the latchoff delay time four times longer than the startup

delay time. Longer latchoff delay times can be achieved by

placing a resistor in parallel with CDLY.

Inductor Selection

The choice of inductance for the inductor determines the

ripple current in the inductor. Less inductance leads to more

ripple current, which increases the output ripple voltage and

conduction losses in the MOSFETs. However, using smaller

inductors allows the converter to meet a specified

peak−to−peak transient deviation with less total output

capacitance. Conversely, a higher inductance means lower

ripple current and reduced conduction losses, but more

output capacitance is required to meet the same

peak−to−peaktransient deviation.

In any multiphase converter, a practical value for the

peak−to−peak inductor ripple current is less than 50% of

the maximum dc current in the same inductor. Equation 4

shows the relationship between the inductance, oscillator

frequency, and peak−to−peak ripple current in the inductor.

IR +

VVID (1 * D)

fSW L

(eq. 4)

As a typical design, the IR should be no bigger than 45% of

the DC current, thus it needs to satisfy:

VVID (1 * D)

fSW L

v 0.45

Imax

(eq. 5)

Solving Equation 5 for for above example, it has:

L w

1.51875 V

(1 * 0.1266)

300 kHz

0.45

69 A

+ 430 nH

For this example, choosing a 450 nH inductor is a good

starting point and gives a calculated ripple current of 9.8 A.

The inductor should not saturate at the peak current of 28 A

and should be able to handle the sum of the power dissipation

caused by the average current of 23 A in the winding and

core loss.

Another important factor in the inductor design is the dc

resistance (DCR), which is used for measuring the phase

currents. A large DCR can cause excessive power losses,

though too small a value can lead to increased measurement

error for current limit and current monitoring. The typical

DCR value is about 0.5 − of 0.8 m

ADP3430 Datasheet(PDF) 16 Page - ON Semiconductor

ADP3430 Datasheet(HTML) 16 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL