THS4281DBVT datasheet(30/43 Pages) TI1

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THS4281

SLOS432B – APRIL 2004 – REVISED OCTOBER 2015

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Layout Guidelines (continued)

device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and

the input impedance of the destination device: this total effective impedance should be set to match the trace

impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can

be series-terminated at the source end only. Treat the trace as a capacitive load in this case, and use a

series resistor (R(ISO) = 10 Ω to 100 Ω, as noted Driving Capacitive Loads) to isolate the capacitive load. If

the input impedance of the destination device is low, there is signal attenuation due to the voltage divider

formed by R(ISO) into the terminating impedance. A 50-Ω environment is normally not necessary onboard,

and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots.

5. Socketing a high-speed part like the THS4281 is not recommended. The additional lead length and pin-

to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it

almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering

the THS4281 onto the board.

10.2 Layout Examples

Figure 76. THS4281EVM Layout (Top Layer and Silkscreen

Figure 77. THS4281EVM Board Layout

Layer)

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THS4281DBVT Datasheet(PDF) 30 Page - Texas Instruments