UPSD3312D datasheet(65/272 Pages) STMICROELECTRONICS

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UPSD33xx

Interrupt system

Doc ID 9685 Rev 7

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13.1.8

PCA interrupt

The PCA has eight interrupt sources, which are logically ORed together when interrupting

the MCU.The ISR must read the flag bits to determine the cause of the interrupt.

●

Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0

respectively.

●

Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1

and INTF0 respectively.

Table 19, Table 18, Table 19, and Table 21 have detailed bit definitions of the interrupt

system SFRs.

Table 19.

IE: Interrupt Enable register (SFR A8h, reset value 00h)

Table 21.

IEA: Interrupt Enable Addition register (SFR A7h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

ET2

ES0

ET1

EX1

ET0

EX0

Table 20.

IE register bit definition

Bit

Symbol

R/W

Function

7EA

R,W

Global disable bit

0 = All interrupts are disabled.

1 = Each interrupt source can be individually enabled or

disabled by setting or clearing its enable bit.

6–

R,W

Do not modify this bit. It is used by the JTAG debugger

for instruction tracing. Always read the bit and write back

the same bit value when writing this SFR.

5(1)

1 = Enable Interrupt, 0 = Disable Interrupt

ET2

R,W

Enable Timer 2 Interrupt

4(1)

ES0

R,W

Enable UART0 Interrupt

3(1)

ET1

R,W

Enable Timer 1 Interrupt

2(1)

EX1

R,W

Enable External Interrupt INT1

1(1)

ET0

R,W

Enable Timer 0 Interrupt

0(1)

EX0

R,W

Enable External Interrupt INT0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EADC

ESPI

EPCA

ES1

–

EI2C–

Table 22.

IEA register bit definition

Bit

Symbol

R/W

Function

7(1)

EADC

R,W

Enable ADC Interrupt

6(1)

ESPI

R,W

Enable SPI Interrupt

5(1)

EPCA

R,W

Enable Programmable Counter Array Interrupt

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