UPSD3312D datasheet(27/272 Pages) STMICROELECTRONICS

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UPSD33xx

UPSD33xx hardware description

Doc ID 9685 Rev 7

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Table 3.

Port type and voltage source combinations

Figure 4.

UPSD33xx functional modules

Device Type

VCC for MCU

module

VDD for PSD

module

Ports 3 and 4 on

MCU module

Ports A, B, C, and D

on PSD module

5 V:

UPSD33xx

3.3 V

5.0 V

3.3 V but 5 V tolerant

5 V

3.3 V:

UPSD33xxV

3.3 V

3.3 V but 5 V tolerant

3.3 V. NOT 5 V tolerant

10-bit

ADC

Dedicated Memory

Interface Prefetch,

Branch Cache

Enhanced MCU Interface

Decode PLD

PSD Page Register

SRAM

CPLD - 16 MACROCELLS

JTAG ISP

Reset Logic

WDT

Internal

Reset

Port 1

Port 3

Dual

UARTs

Interrupt

3 Timer /

Counters

256 Byte SRAM

Turbo 8032 Core

PSD Internal Bus

8032 Internal Bus

PSD

Reset

LVD

Unit

Port D

GPIO

Port C

JTAG and

GPIO

Secondary

Flash

Reset Input

UPSD33XX

JTAG

DEBUG

8-Bit Die-to-Die Bus

Main Flash

PCA

PWM

Counters

Reset

Ext.

Bus

SPI

CC Pins

3.3V

DD Pins

3.3V or 5V

MCU Module

PSD Module

Port 3 - UART0,

Intr, Timers

Port 1 - Timer, ADC, SPI

Port 4 - PCA,

PWM, UART1

Port 3

XTAL

Clock Unit

Port A,B,C PLD

I/O and GPIO

AI07842b

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