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UPSD3312D Datasheet(PDF) 25 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx Pin descriptions Doc ID 9685 Rev 7 25/272 PA0 35 N/A I/O General I/O port pin All Port A pins support: – PLD Macro-cell outputs, or – PLD inputs, or – Latched Address Out (A0-A7), or – Peripheral I/O mode PA1 34 N/A I/O General I/O port pin PA2 32 N/A I/O General I/O port pin PA3 28 N/A I/O General I/O port pin PA4 26 N/A I/O General I/O port pin PA5 24 N/A I/O General I/O port pin PA6 22 N/A I/O General I/O port pin PA7 21 N/A I/O General I/O port pin 1. N/A = Signal Not Available on 52-pin package. Table 2. Pin definitions (continued) Port pin Signal name 80-Pin num. 52-Pin num.(1) In/Out Function Basic Alternate 1 Alternate 2 |
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