L9662 datasheet(68/80 Pages) STMICROELECTRONICS

68 / 80 page

Functional description

L9662

68/80

DocID028325 Rev 1

The following describes the bit usage for both MS & PSI5 Satellite Modes:

Bit [D15]

If during the previous received request a SPI communication

error occurred or invalid message was received, the device shall

set bit D15 indicating that the whole data frame of 80 bit is not

valid.

Bits [D13:D10]

These bits are used to configure the output channels for either

CRC or Parity sensor protocols.

When in MS Mode the default configuration is the protocol A.

For PSI5 mode these bits must be set to 1's.

Bits [D09:D08]

Sync Pulse high time

Bit [D7:D5]

These bits control the configuration of the IF3/V3 pin.

IF2/V2 Output Selection

MS Mode (Prot a\Prot B) Default

PSI5 Mode

MS Mode (Prot a\Prot B) Default PSI5 Mode

Receiver Disable Time Selection

Odd Parity – Includes all 16 bits

Table 36. MOSI MCR bit definition (continued)

Bit

MOSI Command MS – Mode‘D3’=0

MOSI Command PSI5 – Mode‘D3’=1

State

Description

Table 37. Sync pulse high time selections

SPL1

SPL0

Description

20μs (default)

30μs

40μs

80μs

Table 38. Configuration of the IF3/V3 pin

D7/D6

D5/D4

Description

IFx/Vx pin is HiZ

IFx/Vx pin will source an analog current that is 1/100 of

the sensor current

IFx/Vx pin will be a digital output indicating if the current is

above or below the selected threshold. When a channel

(ICHx) is off this pin will be high (~VDD).

L9662 Datasheet(PDF) 68 Page - STMicroelectronics

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