TMS320F28075PZPQ datasheet(49/182 Pages) TI1

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TMS320F28075

www.ti.com

SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015

5.7.3.2.2 Internal Clock Frequencies

Table 5-12 provides the clock frequencies for the internal clocks.

Table 5-12. Internal Clock Frequencies

MIN

NOM

MAX

UNIT

f(SYSCLK)

Frequency, device (system) clock

120

MHz

tc(SYSCLK)

Period, device (system) clock

8.33

500

f(PLLRAWCLK)

Frequency, system PLL output (before SYSCLK divider)

120

400

MHz

f(AUXPLLRAWCLK)

Frequency, auxiliary PLL output (before AUXCLK divider)

120

400

MHz

f(AUXPLL)

Frequency, AUXPLLCLK

MHz

f(PLL)

Frequency, PLLSYSCLK

120

MHz

f(LSP)

Frequency, LSPCLK(1)

120

MHz

tc(LSPCLK)

Period, LSPCLK

8.33

500

See

f(OSCCLK)

Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or X1)

respective

clock

f(EPWM)

Frequency, EPWMCLK(2)

100

MHz

f(HRPWM)

Frequency, HRPWMCLK

100

MHz

(1)

Lower LSPCLK will reduce device power consumption. The default at reset is SYSCLK/4.

(2)

For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

5.7.3.2.3 Output Clock Frequency and Switching Characteristics

Table 5-13 provides the frequency of the output clock. Table 5-14 shows the switching characteristics of

the output clock, XCLKOUT.

Table 5-13. Output Clock Frequency

MIN

MAX

UNIT

f(XCO)

Frequency, XCLKOUT

MHz

Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

tf(XCO)

Fall time, XCLKOUT

tr(XCO)

Rise time, XCLKOUT

tw(XCOL)

Pulse duration, XCLKOUT low

H – 2

H + 2

tw(XCOH)

Pulse duration, XCLKOUT high

H – 2

H + 2

(1)

A load of 40 pF is assumed for these parameters.

(2)

H = 0.5tc(XCO)

Specifications

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