GS1671 datasheet(55/130 Pages) SEMTECH

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GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

55 of 130

EDH CRC errors are only indicated when the device is operating in SD mode and when

the device has correctly received EDH packets.

4.15.4 HD Line Number Error Detection

If a mismatch in the calculated and received line numbers is detected, the LNUM_ERR

bit in the VIDEO_ERROR_STAT_X register is set HIGH.

4.16 Ancillary Data Detection & Indication

The GS1671 detects ancillary data in both the vertical and horizontal ancillary data

spaces. Status signal outputs Y/1ANC and C/2ANC are provided to indicate the position

of ancillary data in the output data streams. These signals may be selected for output on

the multi-function I/O port pins (STAT[5:0]).

The GS1671 indicates the presence of all types of ancillary data by detecting the 000h,

3FFh, 3FFh (00h, FFh, FFh for 8-bit video) ancillary data preamble.

NOTE: Both 8 and 10-bit ancillary data preambles are detected by the device.

By default (at power up or after system reset) the GS1671 indicates all types of ancillary

data. Up to 5 types of ancillary data can be specifically programmed for recognition.

For HD video signals, ancillary data may be placed in both the Y and Cb/Cr video data

streams separately. For SD video signals, the ancillary data is multiplexed and combined

into the YCbCr data space.

When operating in HD mode, the Y/1ANC signal is HIGH whenever ancillary data is

detected in the Luma data stream, and C/2ANC is HIGH whenever ancillary data is

detected in the Chroma data stream. The signals are asserted HIGH at the start of the

ancillary data preamble, and remain HIGH until after the ancillary data checksum.

When operating in SD mode, the Y/1ANC and C/2ANC signals depend on the output

data format. For 20-bit demultiplexed data, the Y/1ANC and C/2ANC signals operate

independently to indicate the first and last ancillary Data Word position in the Luma

and/or Chroma data streams. For 10-bit multiplexed data, the Y/1ANC signal is HIGH

whenever ancillary data is detected, and the C/2ANC signal is always LOW.

These status signal outputs are synchronous with PCLK and may be used as

clock-enables for external logic, or as write-enables for an external FIFO or other

memory devices.

The operation of the Y/1ANC and C/2ANC signals is shown below in Figure 4-21.

NOTE: When I/O processing is disabled, the Y/1ANC and C/2ANC flags may toggle, but

they are invalid and should be ignored.

GS1671 Datasheet(PDF) 55 Page - Semtech Corporation