| Electronic Components Datasheet Search |
|
GS1671 Datasheet(PDF) 32 Page - Semtech Corporation |
|
|
|||||||||||||||||||||||||||||
GS1671 Datasheet(HTML) 32 Page - Semtech Corporation |
|
32 / 130 page ![]() GS1671 HD/SD SDI Integrated Receiver Data Sheet 53737 - 2 September 2012 32 of 130 Once a valid input signal has been detected, the asynchronous lock algorithm enters a “hunt” phase, in which the device attempts to detect the presence of either TRS words or DVB-ASI sync words. By default, the device powers up in auto mode (the AUTO/MAN bit in the host interface is set HIGH). In this mode, the device operating frequency toggles between HD and SD rates as it attempts to lock to the incoming data rate. The PCLK output continues to operate, and the frequency may switch between 148.5MHz, 74.25MHz, 27MHz and 13.5MHz. When the device is operating in manual mode (AUTO/MAN bit in the host interface is LOW), the operating frequency needs to be set through the host interface using the RATE_DET bit. In this mode, the asynchronous lock algorithm does not toggle the operating rate of the device and attempts to lock within a single standard. Lock is achieved within three lines of the selected standard. 4.6.2 Signal Interruption The device tolerates a signal interruption of up to 10 μs without unlocking, as long as no TRS words are deleted by this interruption. If a signal interruption of greater than 10 μs is detected, the lock detection algorithm may lose the current data rate, and LOCKED will de-assert until the data rate is re-acquired by the lock detection block. 4.7 SMPTE Functionality 4.7.1 Descrambling and Word Alignment The GS1671 performs NRZI to NRZ decoding and data descrambling according to SMPTE 292/SMPTE 259M-C and word aligns the data to TRS sync words. When operating in manual mode (AUTO/MAN = LOW), the device only carries out SMPTE decoding, descrambling and word alignment when the SMPTE_BYPASS pin is set HIGH and the DVB_ASI pin is set LOW. When operating in Auto mode (AUTO/MAN = HIGH), the GS1671 carries out descrambling and word alignment to enable the detection of TRS sync words. When two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been detected, the device word-aligns the data to the TRS ID words. TRS ID word detection is a continuous process. The device remains in SMPTE mode until TRS ID words fail to be detected. NOTE: Both 8-bit and 10-bit TRS headers are identified by the device. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |