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AD9531

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS MODE

Output Frequency

400

MHz

Rise/Fall Time (20% to 80%)

160

100 Ω termination across the output pair; listed value is for the

edge (rising or falling) with the lesser rate of change (|δv/δt|)

Duty Cycle

Differential Output Voltage

Swing

Balanced, VOD

247

454

Voltage swing between the output pins; output driver static

Unbalanced, ΔVOD

Absolute difference between the voltage swing of the OUT3_xP pin

and the OUT3_xN pin; output driver static

Offset Voltage

Common-Mode, VOS

1.125

1.26

1.375

Output driver static

Common-Mode

Difference, ΔVOS

Voltage difference between the OUT3_xP pin and the OUT3_xN pin;

output driver static

Short-Circuit Output Current

Output driver static

CMOS MODE

1.8 V Supply

Output Frequency

150

MHz

10 pF load

Rise/Fall Time (20% to

80%)

1.0

10 pF load; listed value is for the edge (rising or falling) with the

lesser rate of change (|δv/δt|)

Duty Cycle

10 pF load

Output Voltage High (VOH)

VDD − 0.2

Relative to VDD3_01 (Pin 66) with output driver static and

IOH = 1 mA

Output Voltage Low (VOL)

0.2

Output driver static and IOL = 1 mA

3.3 V Supply

Output Frequency

200

MHz

10 pF load

Rise/Fall Time (20% to

80%)

0.7

10 pF load; listed value is for the edge (rising or falling) with the

lesser rate of change (|δv/δt|)

Duty Cycle

10 pF load

Output Voltage High (VOH)

VDD − 0.2

Relative to VDD3_3V3 (Pin 67) with output driver static and

IOH = 1 mA

Output Voltage Low (VOL)

0.2

Output driver static and IOL = 1 mA

PLL3 VCO and PFD Characteristics

The specifications in Table 30 apply to both the input and output PLLs of PLL3.

Table 30.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO FREQUENCY

RANGE

720

805

MHz

An additional 200 ppm margin is allowed beyond these limits to accommodate input

reference drift

PLL FIGURE OF

MERIT (FOM)

−215

dBc/Hz

Measured at 100 kHz offset from the output frequency under the following conditions:

fR = 10 MHz (3.3 V CMOS single-ended input), fOUT = 125 MHz (HSTL output)

PFD FREQUENCY

RANGE

9.5

100

MHz

Rev. 0 | Page 18 of 88

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