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Data Sheet

AD9531

PLL1 LOOP CONFIGURATIONS

The selection of the various PLL1 loop configurations depends

on the following three criteria:

•

The fixed delay bits (Register 0x0101, Bits[D6:D5]).

•

The external oscillator (VXCO) mode bits

(Register 0x0101, Bits[D1:D0]).

•

The N1B divider value.

A summary of the criteria necessary to select the various loop

configurations is shown in Table 38.

Table 38. PLL1 Loop Configurations1

N1B

Loop

VCO

Bits[D6:D5]

Bits[D1:D0]

0 or 1

Internal

External

Internal

External

X means don’t care.

PLL1 Loop 1 Configuration (Integrated VCO)

In the Loop 1 configuration, the loop bandwidth of PLL1 is

constant at a nominal value of 100 kHz. The PFD of the PLL

drives a 1.8 V charge pump, which automatically changes its

output current proportional to the value of N1A, thereby

keeping the loop bandwidth constant regardless of the

frequency translation ratio.

The VCO frequency is a function of the PFD input frequency

(see the PLL1 Reference Frequency Scaling section) and the

values programmed into the registers associated with N1A,

N1A fraction, and N1A modulus.













Modulus

N1A

Fraction

N1A

PFD

VCO

where:

fVCO is the frequency of the VCO.

fPFD is the frequency at the input to the PFD.

N1A is an element of the following set: {NMIN, NMIN + 1, ... 255},

where NMIN = 15 for integer-N operation and NMIN = 80 for

fractional-N operation.

N1A Fraction is an element of the following set: {0, 1 ...

1,048,574}.

N1A Modulus is an element of the following set, but with the

constraint of N1A Fraction < N1A Modulus: {1, 2 ... 1,048,575}.

OUT1_x and is an element of the following set: {1, 2 ... 256}.

Note that programming N1A fraction to 0 disables the SDM and

configures PLL1 as an integer-N PLL. Integer-N operation yields

the best performance in terms of phase noise, spurs, and jitter.

The overall frequency translation equation for Loop 1 is as follows:

Modulus

N1A

Fraction

N1A

REF

OUT1













where:

fOUT1 is the frequency at OUT1_x.

fREF is the frequency of the active reference (REF_1A or REF_1B).

R1 is an element of the following set: {½, 1, 4, 5 ... 4,095}. The

value of ½ is the result of selecting the ×2 reference multiplier

(by programming the R1 divider to a value of 0).

M1 is an element of the following set: {3, 4 ... 11}.

D1 is the channel divider (D1A, D1B, or D1C) associated with

LOOP

FILTER

VCO

SDM

÷N1A

÷M1

REF1_Ax

REF1_Bx

OUT1_0x

OUT1_9x

REF1_SEL

RFIN1_x

AD9531: PLL1

1.8V

REFERENCE

INPUT

LDOREG1

Figure 13. PLL1 Loop 1 Configuration

Rev. 0 | Page 31 of 88

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