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AD9531 Datasheet(PDF) 20 Page - Analog Devices

Part # AD9531
Description  3-Channel Clock Generator, 24 Outputs
PDF  88 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9531 Datasheet(HTML) 20 Page - Analog Devices

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AD9531
Data Sheet
SERIAL CONTROL PORT
Table 34.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT (SCLK, SDIO, CS)
1.8 V Supply
DVDD_IO (Pin 18) powered with 1.8 V
Input Voltage
Logic 1
1.3
V
Logic 0
0.6
V
Input Current (IINH, IINL)
−2
+2
µA
Input Capacitance
3
pF
3.3 V Supply
DVDD_IO (Pin 18) powered with 3.3 V
Input Voltage
Logic 1
1.3
V
Logic 0
0.6
V
Input Current (IINH, IINL)
−2
+2
µA
Input Capacitance
3
pF
OUTPUT (SDIO)
1.8 V Supply
DVDD_IO (Pin 18) powered with 1.8 V
Output Voltage
Logic 1
VDD − 0.2
V
1 mA load current
Logic 0
0.2
V
1 mA load current
3.3 V Supply
DVDD_IO (Pin 18) powered with 3.3 V
Output Voltage
Logic 1
VDD − 0.2
V
1 mA load current
Logic 0
0.2
V
1 mA load current
Serial Control Port Timing
Table 35.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
1.8 V SUPPLY
DVDD_IO (Pin 18) powered with 1.8 V
SCLK
Clock Rate, 1/tSCLK
50
MHz
Pulse Width High, tHIGH
2.1
ns
Pulse Width Low, tLOW
1.7
ns
SDIO to SCLK Setup, tDS
0.3
ns
SCLK to SDIO Hold, tDH
1.0
ns
SCLK to Valid SDIO, tDV
6.5
ns
CS to SCLK Setup (tS) and Hold (tH)
1.1
ns
CS Minimum Pulse Width High
1.4
ns
3.3 V SUPPLY
DVDD_IO (Pin 18) powered with 3.3 V
SCLK
Clock Rate, 1/tSCLK
50
MHz
Pulse Width High, tHIGH
0.8
ns
Pulse Width Low, tLOW
2.5
ns
SDIO to SCLK Setup, tDS
1.8
ns
SCLK to SDIO Hold, tDH
0.4
ns
SCLK to Valid SDIO, tDV
6.5
ns
CS to SCLK Setup (tS) and Hold (tH)
2.4
ns
CS Minimum Pulse Width High
3.0
ns
Rev. 0 | Page 20 of 88



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