UT04VS33P datasheet(10/21 Pages) AEROFLEX

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FUNCTIONAL DESCRIPTIONS

Voltage Inputs

Monitoring of supply levels is done at the VINx pins. Based on

the mode of operation (TH0, TH1, OVSH state), the monitored

voltage is connected directly to the pin or via a resistive divider.

These connections are described further in the Determining a

Channel Detection Threshold section.

RESETS

The (RESET and RESETB) outputs respond to changes in the

state of the enabled channels (either an ENx signal going to the

enabled state or a VOUTx signal, of an enabled channel, chang-

ing state) and to changes in the master, MRB pin. Timing val-

ues are given in the AC Characteristics table and in Figures 4,5

and 6. These pins are digital output open drain having an active

pull-down device, with drive information given in the DC

Characteristics table.

Outputs

The VOUTx pins indicate the state of the corresponding supply

monitor input source. When the input level is in a valid region,

based on the mode and threshold settings, the VOUTx pin is in

the logic 1 state. If the channel is disabled or the input level is

invalid, the VOUTx pin is in the logic 0 state. In addition, when

in over-voltage detect mode (OVSH=1), VOUT3 and VOUT4

are inactive. The INV function, when set to logic 1, inverts the

sense of the VOUT3 and VOUT4 pins. There are several timing

parameters associated with the state transitions which are de-

scribed in the Determining a Channel Detection Threshold sec-

tion. Values for drive and timing are in the DC and AC

Characteristics tables.

Thresholds/Over-Voltage Setting/Tolerance

Thresholds are determined by several pin settings, TH0, TH1,

OVSH and TOL. The variations in operation and setup of the

channel inputs, including external components, are described

below. The setting of the OVSH pin determines the threshold

detection mode for the four channels. When logic 0, all four

channels sense when the corresponding input falls below the as-

sociated threshold, the under-voltage condition (see Determin-

ing a Channel Detection Threshold). In this mode when the

signal level falls below the threshold, the corresponding VOUT

is switched to logic 0, after a fixed time delay. When the signal

returns to a level above the threshold and after the default or

user defined delay, (see the CDLY timing section), the VOUT

output is switched to the logic 1 state, indicating a valid level

(see Figure 6).

For the mode when OVSH is logic 1, over- and under-voltage

detection, the input threshold for channels 1 and 2 are handled

in the same fashion as for the previously described mode. In this

mode, the channel 3 and 4 inputs are checked for an over-volt-

age condition in conjunction with the voltage monitored on

channel 1 and channel 2, respectively. Also, threshold levels are

determined differently, see the section on Determining a Chan-

nel Detection Threshold and Tables 1A and 1B. The under-

voltage condition from channel 1 and the over-voltage condi-

tion detected by channel 3 are combined to indicate the occur-

rence of either condition at the channel 1 output. Likewise,

conditions for channel 2 and 4 are combined and indicated at

the channel 2 output. Note: When OVSH is logic 1, disabling

channel 1 or 3 forces VOUT1 to logic 0. The same is true for

VOUT2, with respect to the enables for channels 2 and 4. How-

ever, only CDLY1 and CDLY2, respectively, are utilized for

output timing.

Determining Channel Detection Threshold

For the case of under-voltage sensing utilizing the preset

thresholds (TH1 and TH0 both not being logic 1), the actual

threshold is based on the nominal threshold levels as shown in

Table 2. The actual threshold voltage, accounting for tolerance,

based on the TOL pin setting and circuit variations, is given by

the following equation (values also listed in the DC Character-

istics table):

Vth_actual(nom) =

Vthresh_nominal * [1 - 5% *(1 + TOL) - 2.5%]

where Vthresh-nominal is given in Table 2, TOL is 0 when log-

ic 0 and 1 when logic 1, and 2.5% accounts for circuit varianc-

es.

For adjustable under-voltage thresholds, when TH0 = TH1 =

logic 1, and over-voltage sensing on the channel 3 and 4 inputs

when OVSH = logic 1, the over-voltage (Vth_adj-overV)

thresholds are determined by user-implemented resistive divid-

ers placed at the input to the given channel. These threshold lev-

els are determined by the following equation:

Vth_adj-overV = [(RT + RB)/RB +/- 2.5%] * VRFTH

where RT is the top resistor of the divider and RB is the lower

resistor tied to VSS, 2.5% accounts for circuit variances and

VRFTH is an internally-generated reference voltage with value

as given in the DC Characteristics table. Note: The TOL pin

function is not applicable in these modes. In addition to the

2.5% added to account for circuit variations, the user should

consider resistor and supply variation tolerances when calculat-

ing the values for the resistive divider. Other considerations for

the choice of resistor values are power consumption and time

delay impact. The nominal capacitance of the input channel is

given in the DC Characteristics table.

Note: The maximum level at any analog channel input is limit-

ed to 3.6V. This limits the maximum voltage level of the mon-

itored signal. When the device is placed in the adjustable

threshold state (TH0 = TH1 = logic 1) utilizing an external re-

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