6

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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

Symbol Parameters

Condition

Min.

Type Max.

Units

V

IH

Single-ended inputs, except SMBus, SADR_tri

0.65 V

DD

V

V

V

IM

SADR_tri

0.4 V

DD

0.6 V

DD

V

V

IL

Single-ended inputs, except SMBus, SADR_tri

-0.3

0.35 V

DD

V

V

H

V

0.05 V

DD

0.2 V

DD

V

V

OH

Single-ended outputs, except SMBus. I

-2mA

V

DD

-0.45

V

V

OL

Single-ended outputs, except SMBus. I

-2mA

0.45

V

I

IN

Single-ended inputs, V

(exclude XTAL_IN pin)

-5

5

uA

I

INP

Single-ended inputs

V

V

resistors

-200

200

uA

fin

XTAL, or XTAL_IN

23

25

26

MHz

Lpin

7

nH

C

IN

Control Inputs

1.5

5

pF

Cout

Output pin capacitance

6

pF

t

STAB

Clock output Stabiliza-

From V

stabilization or de-assertion of CKPWRGD_

PD# to 1st clock

0.6

1

ms

f

MODIN

Input SS Modulation

Allowable Frequency

(Triangular Modulation)

30

31.500 33

kHz

t

LATOE#

CLK start after OE# assertion

CLK stop after OE# deassertion

1

3

clocks

t

DRVPD

CLK output enable after

CKPWRGD_PD# de-assertion

300

us

t

F

Control inputs

5

ns

t

R

Control inputs

5

ns

V

ILSMB

SMBus Input Low Volt-

0.8

V

V

IHSMB

SMBus Input High Volt-

2.1

3.6

V

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions Cont...

16-0064