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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

Electrical Characteristics–Phase Jitter Parameters

(T

o

C; VDD = 3.3V+/-10%; VDDO = 3.3V+/-10%; VDDO = 2.5V+/-10%; VDDO = 1.8V+/-10%, See Test Loads

for Loading Conditions)

Symbol Parameters

Condition

Min. Type

INDUSTRY

LIMIT

Units

t

jphPCIeG1

Phase Jitter, PLL

Mode

34

86

ps

(p-p)

t

jphPCIeG2

0.9

3

ps

(rms)

PCIe Gen 2 High Band 1.5MHz < f < Nyquist

2.2

3.1

ps

(rms)

t

jphPCIeG3

0.5

1

ps

(rms)

t

jphSGMII

125MHz, 1.5MHz to 20MHz, -20dB/decade rollover <

1.9

NA

ps

(rms)

t

jphPCIeG1

Additive Phase

Jitter,

Bypass Mode

0.6

N/A

ps

(p-p)

t

jphPCIeG2

0.1

N/A

ps

(rms)

PCIe Gen 2 High Band 1.5MHz < f < Nyquist

0.05

N/A

ps

(rms)

t

jphPCIeG3

0.05

N/A

ps

(rms)

t

jphSGMII

125MHz, 1.5MHz to 10MHz, -20dB/decade rollover <

0.15

N/A

ps

(rms)

Note:

1. Applies to all outputs, with device driven by a clean clock source.

2. See http://www.pcisig.com for complete specs

3. Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

4. Subject to final ratification by PCI SIG.

5. For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

6. Applies to all differential outputs

16-0064