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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics

(T

o

C; VDD = 3.3V+/-10%; VDDO = 3.3V+/-10%; VDDO = 2.5V+/-10%; VDDO = 1.8V+/-10%, See Test Loads

for Loading Conditions)

Symbol Parameters

Condition

Min.

Type

Max.

Units

t

DC

Measured differentially, PLL Mode

45

55

%

t

DCD

Measured differentially, Bypass Mode@100MHz -1

0

1

%

t

pdBYP

Bypass Mode, VT = 50%

2500

4500

ps

t

pdPLL

PLL Mode VT = 50%

-250

250

ps

t

skew

VT = 50%

25

50

ps

t

jcyc-cyc

PLL mode @100MHz output

50

ps

Additive Jitter in Bypass Mode @100MHz

output

0.1

25

ps

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Measured from differential waveform

3. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

4. All outputs at default slew rate

5. The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.

o

C; See Test Loads for Loading Conditions)

Symbol Parameters

Condition

Min.

Type

Max.

Units

I

DDAOP

VDDA+VDDR, PLL Mode, @100MHz, typical

value under VDDO = 1.8V

37

45

mA

I

DDOP

VDD1.8, All outputs active @100MHz, typical

value under VDDO = 1.8V

52

60

mA

I

DDAPD

VDDA+VDDR, PLL Mode, @100MHz

1

mA

I

DDPD

VDD1.8, Outputs Low

1.8

mA

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Input clock stopped.

16-0064