MB9B110T datasheet(85/129 Pages) SPANSION

85 / 129 page

Da t a S h e e t

MB9B110T-DS706-00016-3v0-E, January 31, 2014

CONFIDENTIAL

(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)

Parameter

Symbol

Value

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

100

μs

PLL input clock frequency

FPLLI

MHz

PLL multiple rate

75 multiple

PLL macro oscillation clock frequency

FPLLO

200

300

MHz

Main PLL clock frequency*

FCLKPLL

144

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

(4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR)

(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)

Parameter

Symbol

Value

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

100

μs

PLL input clock frequency

FPLLI

3.8

4.2

MHz

PLL multiple rate

71 multiple

PLL macro oscillation clock frequency

FPLLO

190

300

MHz

Main PLL clock frequency*

FCLKPLL

144

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency

has been trimmed.

divider

PLL input

clock

Main

PLL

PLL macro

oscillation clock

divider

Main PLL

clock

(CLKPLL)

divider

Main PLL connection

High-speed CR clock (CLKHC)

Main clock (CLKMO)

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