LM98722CCMTSLASHNOPB datasheet(21/150 Pages) TI1

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LM98722

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SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

7.3.10.3 SSCG Configuration/Usage Flow

•

Unlock Registers (Page 0, Register 0, Bit 0 = 0)

•

Ensure PIXCLK/ADCCLK Configuration is set to ADCCLK. Page 0, Register 0x02, Bit 2 = 0.

•

Set Override PLL2 Lock Detector (Page 2, Register 0x1B, Bit 4) = 1

•

Set PLL2 Charge Pump Current Control (Page 2, Register 0x19, Bits 4:3) = 00

•

Set PLL2 Filter Bandwidth Control (Page 2, Register 0x19, Bits 2:0) = 111

•

Set SSCG Spread Boost (Page 2, Register 0x1A, Bit 5) = 0 or 1 (0 = default, recommended for most

applications)

•

Set SSCG Spread Gain (Page 2, Register 0x1A, Bit 4) = 0 or 1 (0 = default, recommended for most

applications)

•

Set SSCG Spread Width (Page 2, Register 0x1A, Bits 3:2) = 0.625% to 2.5% (Beyond 2.5% most LVDS

deserializers will not track the clock properly)

•

Set SSCG SH Sync Enable (Page 2, Register 0x1A, Bit 1) = 0 or 1 (Set to 1 for Spread All)

•

Set PLL Mode Select (Page 2, Register 0x1B, Bits 1:0) = 00, 01 or 11. Spread Output Only or Spread All

Clocks

•

If PLL Clock Multiplication Enabled, Set Clock Mult M (Page 2, Register 0x1C) and N (Page 2, Register 0x1D)

to desired values. If a pixel rate clock is applied, set the PLL multiplication to the same factor as the AFE

Mode selected at Page 0, Register 0x03, Bits 7:6. ie. The multiplication factor should be 3x for Mode 3, 2x for

Mode 2 and 1x for Mode 1.

•

Set SSCG Enable (Page 2, Register 0x1A, Bit 0) = 1 (enable spreading, load spreading state machines)

•

Lock Registers (Page 0, Register 0, Bit 0 = 1)

•

If spreading is synchronized to SH interval, the spreading function will wait until the next SH Interval before

beginning.

7.3.10.4 Changing SSCG Settings

To change SSCG settings:

•

Un-Lock Registers ((Page 0, Register 0, Bit 0 = 0)

•

Set SSCG Enable = 0 (disable spreading)

•

Change desired SSCG settings.

•

Set SSCG Enable = 1 (enable spreading, reload spreading state machines)

•

Lock Registers (Page 0, Register 0, Bit 0 = 1)

Table 2. SSCG and Clock Multiplication Register Settings

PAGE

DEFAULT

BITS

NAME

DESCRIPTION

Master PLL Range Setting for PLL1 and

1111 1000

[7:5]

PLL2 when

Autorange is off. Set to 111.

[4:3]

PLL1 Charge Pump Current Control

PLL Control 1

Default = 11

[2:0]

PLL1 Filter Bandwidth Control

Default = 000

0001 1000

[7:5]

Reserved

Default = 000

[4:3]

PLL2 Charge Pump Current Control

Default = 11

PLL Control 2

Set to 00 when using SSCG.

[2:0]

PLL2 Filter Bandwidth Control

Default = 000

Set to 111 when using SSCG.

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