LM98722CCMTSLASHNOPB datasheet(4/150 Pages) TI1

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LM98722

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

www.ti.com

Pin Descriptions(1)

I/O

TYP

RES

DESCRIPTION

NO.

NAME

PHIC2

Configurable high speed sensor timing output.

PHIC1

Configurable high speed sensor timing output.

SH1

Configurable low speed sensor timing output.

Chip Serial Interface Address Setting Input

CE LEVEL

ADDRESS

Float

DGND

CAL

Initiate calibration sequence. Leave unconnected or tie to DGND if unused.

RESET

Active-low master reset. NC when function not being used.

SH_R

External request for an SH interval.

SDI

Serial Interface Data Input.

SDO

Serial Interface Data Output.

SCLK

Serial Interface shift register clock.

SEN

Active-low chip enable for the Serial Interface.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

VREFB

Bottom of ADC reference. Bypass with a 0.1

μF capacitor to ground.

VREFT

Top of ADC reference. Bypass with a 0.1

μF capacitor to ground.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

Input Clamp Voltage. Normally bypassed with a 0.1

μF , and a 4.7μF capacitor to

VCLP

AGND. An external reference voltage may be applied to this pin.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

IBIAS

Bias setting pin. Connect a 9.0 k

Ω 1% resistor to AGND.

AGND

Analog ground return.

OSR

Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSG

Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSB

Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1

μF capacitor to

CPOFILT2

CPOFILT1.

DGND

Digital ground return.

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1

μF capacitor to

CPOFILT1

CPOFILT2.

DVB

Digital Core Voltage bypass. Not an input. Bypass with 0.1

μF capacitor to DGND.

Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is

INCLK+

selected when pin 33 is held at DGND, otherwise clock is configured for LVDS

operation.

INCLK-

Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.

DOUT7/

Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS

Mode.

TXCLK+

DOUT6/

Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS

Mode.

TXCLK-

(1)

(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down

with an internal resistor.).

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