USBN9604SLB datasheet(49/60 Pages) NSC

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7.0 Register Set (Continued)

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For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this

endpoint.

This bit is reset to 0 by reading the RXSx register.

SETUP

This bit indicates that the setup packet has been received. It is cleared when this register is read.

RX_ERR

Receive Error. When set, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set, the firmware must flush

the respective FIFO.

7.2.25

Receive Command X Register (RXC1, RXC2, RXC3)

Each of the receive endpoints (2, 4 and 6) has one Receive Command register with the bits defined below.

RX_EN

Receive Enable. OUT packet cannot be received after every data packet is received, or when a STALL handshake is re-

turned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always

be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been re-

ceived with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns

an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE

should be generated.

IGN_SETUP

Ignore SETUP Tokens. When this bit is set, the endpoint ignores any SETUP tokens directed to its configured address.

FLUSH

Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both

the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after re-

ceiving is completed.

RFWL1-0

Receive FIFO Warning Limit. These bits specify how many more bytes can be received to the respective FIFO before an

overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning

limit, the RXWARN bit in the FWEV register is set.

Table 9. Set Receive FIFO Warning Limit

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Reserved

RFWL1-0

Reserved

FLUSH

IGN_SETUP

Reserved

RX_EN

-0

r/w

RFWL Bits

Bytes Remaining in FIFO

RFWL disabled

≤ 4

≤ 8

≤ 16

USBN9604SLB Datasheet(PDF) 49 Page - National Semiconductor (TI)

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