ADC12DL040

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

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The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and

These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before

conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

DF/DCS

Duty cycle stablization and output data format are selectable using this quad state function pin. When enabled,

duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 20% to 80% and generate

a stable internal clock, improving the performance of the part. The Duty Cycle Stabilizer circuit requires a fast

clock edge to produce the internal clock, which is the reason for the rise and fall time requirement listed in the

specifications table.

DF/DCS = 0 the output data format is 2's complement and duty cycle stabilization is applied to the clock. With

DF/DCS is floating, the output data format is offset binary and duty cycle stabilization is not used. While the

sense of this pin may be changed "on the fly," doing this is not recommended as the output data could be

erroneous for a few clock cycles after this change is made.

MULTIPLEX

With the MULTIPLEX pin at a logic low, the digital output words from channels A and B are available on separate

digital output buses (Parallel mode). When MULTIPLEX is high, the digital output words are multiplexed on pins

DA0:DA11 (Multiplex Mode). The DB0/ABb pin changes synchronously with the multiplexed outputs, and is high

when channel A data is present on the outputs, and low when channel B data is present.

OUTPUTS

The ADC12DL040 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at

these outputs while the OE and PD pins are low. In the parallel mode, the data should be captured with the CLK

signal. Depending on the setup and hold time requirements of the receiving circuit (ASIC), either the rising edge

or the falling edge of the CLK signal can be used to latch the data. Generally, rising-edge-capture would

maximize setup time with minimal hold time; while falling-edge-capture would maximize hold time with minimal

setup time. However, actual timing for the falling-edge case depends greatly on the CLK frequency and both

cases also depend on the delays inside the ASIC. Refer to the Tod spec in AC Electrical Characteristics.

In Multiplex mode, both channel outputs are available on DA0:DA11. The ABb signal is available to de-multiplex

the output bus. The ABb signal may also be used to latch the data in the ASIC thus avoiding the use of the CLK

signal altogether. However, since the ABb signal edges are provided in-phase with the data transitions, generally

the ASIC circuitry would have to delay the ABb signal with respect to the data in order to use it as the clock for

the capturing latches. It is also possible to use the CLK signal to latch the data in the multiplexed mode as well -

as described in the previous paragraph.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series resistors of about 100

Ω at the digital

outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the

output currents, which could otherwise result in performance degradation. See Figure 37.

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