-

+

U2B

-

+

U1A

5k, 1%

R1, 1%

R5, 1%

R2, 1%

5k, 1%

2.4k

5k, 1%

5k, 1%

-

+

U1B

-

+

U2A

5k, 1%

R3, 1%

R6, 1%

R4, 1%

5k, 1%

2.4k

5k, 1%

2V

51

51

to

to

39 pF

#

SIGNAL

INPUT

51

*

*

*

*

*

39 pF

#

V

V

ADC12DL040

www.ti.com

SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013

Amplifiers: two LMH6622s or LMH6655s

* – The ground connections indicated with an "*" should be connected to a common point in the analog ground plane.

# – The 39 pF capacitors between the two inputs are for Nyquiest applications and should be removed for

undersampling applications.

Figure 39. Differential Drive Circuit of Figure 37

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series

inductance.

As is the case with all high-speed converters, the ADC12DL040 is sensitive to power supply noise. Accordingly,

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12DL040 between these areas, is required to

achieve specified performance.

The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12DL040's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

Digital circuits create substantial supply and ground current transients. The logic noise thus generated could

have significant impact upon system noise performance. The best logic family to use in systems with A/D

converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the

74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest

supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.

The effects of the noise generated from the ADC output switching can be minimized through the use of 100

Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

Copyright © 2005–2013, Texas Instruments Incorporated

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